Analog Mixed-Signal (AMS) Verification Engineer (H/F)

La mission

ELSYS Design is a European engineering company specialized in electronics, embedded systems, software and complex systems design. As part of the ADVANS Group, ELSYS Design works with major industrial players across Europe. As part of its international expansion, ELSYS Design is reinforcing its presence in Italy, a strategic market for industrial electronics, automotive, semiconductors and energy sectors. Mission description We are looking for a Microelectronics engineer with a first successful experience in Analog Mixed-Signal (AMS) Verification at IP or SoC level to reinforce our teams in Milan, ITALY. Here are all your responsibilities: Verification activities Define and develop AMS verification plans aligned with design specifications Contribute to mixed-signal test bench development (SystemVerilog / Verilog-AMS) Execute simulation campaigns and validate results Modeling & simulation Develop behavioral models (Verilog-A / Verilog-AMS, RNM) Perform co-simulation of analog (SPICE) and digital (RTL) environments Validate performance across PVT conditions Analysis & debugging Analyze simulation results and identify issues Debug mixed-signal interactions Support verification closure through coverage metrics Engineering contribution Participate in verification environment setup Contribute to automation using scripting tools (Python, Tcl, etc.) Work closely with analog, digital and layout teams Technical Environment Languages: Verilog-AMS, Verilog-A, SystemVerilog Tools: Cadence Virtuoso, Spectre, AMS Designer Scripting: Python, Tcl, Perl Domains: ASIC, SoC, mixed-signal systems