Analog IC Layout Engineer – FinFET Technologies (H/F)

La mission

ADVANS Group in Portugal is looking for experienced Analoc IC Layout Engineers to work in the semiconductor industry in our new Lisbon offices. Key Responsibilities: • Design and implement analog IC layouts including floor planning, integration, area estimation, and abstract view generation • Perform placement and routing at block, top, and full-chip levels in the Cadence Virtuoso environment • Develop and layout I/O structures, ESD protection, PADs, and seal rings following advanced node constraints • Execute and debug physical verification checks including DRC, LVS, ERC, and antenna rule checks using industry-standard tools (Assura, PVS, Calibre) • Conduct parasitic and electromigration (EM) extractions, and collaborate closely with Analog Design Engineers to ensure performance and reliability • Address and optimize FinFET-specific challenges, including layout-dependent effects (LDE), double-patterning, DFM, and reliability constraints in nodes below 10nm